Design of large scale electrical circuits is frequently automated by provision of a library of standard cells for performing various circuit functions. In typical large scale circuits (also referred to as VLSI circuits), standard cell circuitry typically occupies from 50% to 70% of the circuit area, with the remainder being memory. Most of the power consumption (both switching power and leakage power) is in the standard cell circuitry.
Cell library functions can include, for example, logic functions such as AND2 (a 2-input AND gate) and OR4 (a 4 input OR gate) and switching functions such as DFF (a D flip-flop). Inverters, NAND gates and NOR gates are also typically included in cell libraries. A standard cell library typically provides multiple cells having the same cell function (e.g., AND2) and differing in drive strength (e.g., AND1×2, AND2×2, etc.). Cells having higher drive strength generally consume more electrical power, but can be used to drive a larger load, or can be used to improve circuit speed.
For example, FIG. 1 schematically shows cell delay as a function of load for a set of cells performing the same function but having different drive strengths, labeled ×1, ×2, ×3, and ×4. By increasing drive strength for a fixed delay, as shown by line 102, a larger load can be driven. By increasing drive strength for a fixed load, as shown by line 104, delay can be reduced. Thus, provision of several cells having different drive strength for performing a certain function provides design flexibility in the cell library. Indeed, a cell-level design is largely a determination of which drive strength to use for each cell function required in a circuit.
Large scale circuit design is frequently formulated as a minimization of power consumption subject to constraints on circuit-level delay, which lead ultimately to constraints on cell-level delay. The relation between circuit-level delay and cell-level delay is generally complex, and is usually accounted for by an automated design tool used in the design process. One example of the complexity in relating cell-level delay to circuit-level delay is that increasing the drive strength of a particular cell Z decreases its delay, but tends to increase the load on the cell(s) Y providing input to cell Z. The increased load on cell(s) Y tends to increase their delay.
For the purposes of this description, “delay” can be a rise delay or a fall delay, or any combination thereof (e.g., an average of rise delay and fall delay). A delay can also be a switching time, or any other cell timing parameter which decreases as cell speed increases. Delays can be state-dependent (e.g., a delay from input A to output Z can depend on the state of a second input B).
For convenience in cell library design and cell layout, the drive strengths for each cell function are usually selected to provide a predetermined scaling of total transistor active area within a cell. For example, the ×2 cell typically has twice the transistor active area of the ×1 cell (with similar scaling for the other drive strengths). The ×2 cell is also often designed to have twice the physical area of the ×1 cell (also with similar scaling for the other drive strengths), in order to simplify cell layout. For example, if the ×1 cell is regarded as a “brick”, then cell layout is simplified if all the larger cells have the configuration of 2 or more adjacent “bricks”. An example of such a configuration is schematically shown on FIGS. 2a and 2b, corresponding to an ×1 and an ×2 cell respectively. On FIG. 2a, a cell 202 includes a transistor having a gate contact 206 between a source 204 and a drain 208. FIG. 2b shows a cell 210 that is twice as large as cell 202, and includes a transistor having a gate contact 214 between a source 212 and a drain 216. The width of the transistor of cell 210 is twice the width of the transistor of cell 202, and thus has twice the active area. For cells having multiple transistors, typically all of the transistors in the cell are scaled together to provide the various drive strengths.
However, the conventional approach to providing cells having varying drive strength described above suffers from a notable drawback, in that significant cell over-design often occurs in practice. This drawback is best appreciated in connection with FIG. 3, which shows a typical distribution of cell drive strength in a large scale circuit. A noteworthy feature of FIG. 3 is that the number of cells is a steeply decreasing function of drive strength. Although the relation between circuit level delay and cell level delay is complex, as indicated above, the design automation tool is ultimately faced with a requirement to select a cell from a finite set of cells having different drive strengths, and usually selects the smallest possible cell to minimize power.
This quantization (or granularity) of cell drive strengths inherently leads to over-design. For example, if a delay corresponding to a drive strength of ×1.1 is required, and the choices are ×1 and ×2, ×2 will be chosen in order to meet the requirement. Similarly, if a drive strength of ×1.9 is required, and the choices are between ×1 and ×2, ×2 will be chosen. In the latter case, the over-design entailed by use of ×2 where ×1.9 would suffice is much less than in the former case, where ×2 is used where ×1.1 would suffice. On FIG. 3, the number of cells is a steeply decreasing function of drive strength, and it is therefore likely that most of the ×2 cells are in fact significantly over-designed (i.e., more like the ×1.1 example above than the ×1.9 example above).
In the example where only an ×1.1 cell was needed and an ×2 cell had to be selected due to drive strength quantization, power consumption is unnecessarily increased by the difference in power consumption between an ×2 cell and an ×1.1 cell. Both switching power and leakage power are undesirably increased by such quantization. Some known design approaches inherently avoid this quantization problem, by reliance on continuous scaling of cell drive strength and/or transistor size during design. These approaches also have their drawbacks. More particularly, such approaches tend to complicate the design process and undesirably increase design time. In other words, the advantage in design simplicity offered by cell library design is partially (or even completely) lost because of further optimization required after the cell level design is complete.
For example, U.S. Pat. No. 4,827,428 considers a method for design optimization where it is assumed that transistor size (i.e., drive strength) can be continuously varied. While such an approach inherently avoids over-design due to quantization, the assumed continuous scalability of transistor sizes is also inherently much more complicated than design with standard library cells having quantized drive strengths.
It should also be noted that many prior art references are concerned with aspects of large scale circuit design independent from the over-design problem identified above. This is not surprising, since large scale circuit design is highly complex, and can therefore be approached from many different and unrelated viewpoints. For example, U.S. Pat. No. 5,724,250 considers detailed methods and algorithms for efficient cell substitution of library cells having different drive strength in a circuit design. Such substitution algorithms do not address the quantization over-design issue identified above. As another example, U.S. Pat. No. 6,496,965 considers provision of variable drive strength cells by automatically wiring 2 or more standard cells together in parallel. While this is an alternative to providing ×1, ×2, etc. cells in the library, wiring cells together in parallel does not address the quantization over-design issue identified above.
Another approach is considered in U.S. Pat. No. 5,633,805, where a cell library having a two-dimensional cell sizing progression is considered, where minimum load and maximum load are treated as independent variables. In U.S. Pat. No. 5,598,347, cell libraries having cells with different drive strength but the same width are considered. Similarly, U.S. Pat. No. 5,663,662 considers a cell library having cells with different drive strength but the same physical area and terminal locations. These three approaches are also concerned with providing solutions to design problems other than the above-identified quantization over-design issue.
Accordingly, it would be an advance in the art to provide a cell library enabling reduced quantization over-design in cell level design. It would also be an advance in the art to provide such reduced over-design without adding significant complexity to the overall circuit design process.